FIG. 1 shows an array substrate, which comprises a common electrode 10, a common electrode line 20, a thin film transistor 30 and a pixel electrode 40, and the common electrode 10 is electrically connected to the common electrode line 20. An etch stop layer 31 and a passivation layer 50 are provided between a layer where the common electrode 10 is located and a layer where the common electrode line 20 is located. To electrically connect the common electrode 10 with the common electrode line 20, a via 60 can be formed above the common electrode line 20, while forming the common electrode 10 by depositing, a layer of common electrode material is also formed on side walls and a bottom side (i.e. an upper surface of the common electrode line 20) of the via 60, the common electrode material inside the via 60 is formed as a connection portion 70 for electrically connecting the common electrode line 20 with the common electrode 10. As the passivation layer 50 and the etch stop layer 31 have relatively large thicknesses, when the connection portion 70 is formed, a breach is likely to be formed on the side wall of the via 60, resulting in poor connection between the common electrode line 20 and the common electrode 10.
Therefore, how to prevent the poor connection between the common electrode line 20 and the common electrode 10 has become a technical problem to be solved urgently in the art.